1. Field of the Invention
The present invention relates to semiconductor fabrication, and in particular to silicon-on-insulator (SOI) device fabrication.
2. Description of the Related Art
Silicon-on-insulator (SOI) technology has become an increasingly important technique utilized in the fabrication and production of semiconductor devices. SOI technology deals with the formation of transistors in a relatively thin monocrystalline semiconductor layer, which overlays an insulating layer. The insulating layer is typically formed on an underlying substrate, which may be silicon. In other words, the active devices are formed in a thin semiconductor on insulator layer rather than in the bulk semiconductor of the device. Currently, silicon is most often used for this monocrystalline semiconductor layer in which devices are formed. However, it will be understood by those skilled in the art that other monocrystalline layers such as germanium or gallium arsenide may be used. Accordingly, any subsequent reference to silicon will be understood to include any semiconductor material.
High performance and high-density integrated circuits are achievable by using the SOI technology because of the reduction of parasitic elements present in integrated circuits formed in bulk semiconductors. Since SOI structures significantly alleviate parasitic elements, and increase the junction breakdown tolerance of the structure, the SOI technology is well suited for high performance and high-density integrated circuits. SOI technology also exhibits its advantages for higher speed, lower power consumption and better radiation immunity due to the enhanced isolation of buried oxide layers.
FIGS. 1-2 partially illustrate a related art SOI device 10. As shown in FIG. 1, a schematic top view of a part of the SOI device 10 is illustrated. The SOI device 10 includes a plurality of transistors 104, 106, 108 and 110 formed thereon, isolated from each other by an insulating layer 102. In addition, two word lines 112 and 114 are provided over the insulating layer 102, respectively crossing over a pair of the SOI transistors. Source/drain regions S/D are formed on opposing sides of the word lines 112 and 114 in each of the SOI transistors 104, 106, 110 and 112. The word line 112 protrudes over the insulating layer 102 and overlies the transistors 104, 106 and a portion of the insulating layer 102 between and adjacent thereto, and the word line 114 protrudes over the insulating layer 102 and overlies the transistors 108, 110 and a portion of the insulating layer 102 between and adjacent thereto. As shown in FIG. 1, the transistors 104, 106, 108 and 110 can be, for example, N-type or P type MOS transistors for defining two MOS transistor arrays in regions 116 and 118 over the SOI device 10, which are shown as dotted lines in FIG. 1, respectively. The MOS array in regions 116 and 118 can function as a PMOS array, an NMOS array or a CMOS array and depends on actual circuit design of the SOI device 10.
FIG. 2 illustrates a cross section taken along line 2-2 of FIG. 1. As shown in FIG. 2, the SOI transistors 104, 106, 108, 110 are respectively formed of a gate dielectric layer 206 stacked on a silicon island 204. The silicon islands 204 are formed on an insulating layer 202 over a base substrate 200, for example a silicon substrate. The silicon islands 204 are electrically isolated from each other by the insulating layer 102 surrounding thereto. Typically, the insulating layer 102 protrudes over the top surface of the silicon island and a recess R is defined over each of the transistors. Referring to the FIG. 2, the word lines 112 and 114 respectively overlie the gate dielectric layer 206 of a pair transistors of the SOI transistors 104, 106, 108 and 110, filling each of the recesses R therein and protruding over the surface between and adjacent to the transistors. With the trend toward size reduction of transistors such as the transistors 104, 106, 108 and 110, a finer spacing is required between the regions 116 and 118. As shown in FIG. 2, since the word lines 112 and 114 protrude over the insulating layer 102, reducing a spacing d1 between the adjacent transistors formed in the regions 116 and 118 is problematic in view of shorting issues which may be caused by the portion of the wordlines 112 and 114, thus size reduction of an SOI device formed over the SOI device 10 and increase of device density thereon is inhibited.
Based on the foregoing, the inventors have thus concluded that a need exists for a silicon-on-insulator (SOI) device capable of eliminating the described line shorting issue of the related art SOI devices. Additionally, the inventors have concluded that this problem can be solved with an improved SOI device and associated fabrication methods, which are disclosed herein, which additionally leads to improvements in process and reliability for such a device.